1. Field of the Invention
The present invention relates to a column redundancy circuit. More particularly, it relates to a column redundancy circuit which performs a column repair operation of a semiconductor memory element at a high-speed.
2. Description of the Prior Art
Generally, under the condition that even one cell among a plurality of fine cells constituting a dynamic random access memory (DRAM) is defective, the DRAM cannot perform a normal function. Therefore, in this case, a redundancy method that the defective cell is replaced with a spare memory cell previously mounted into the DRAM in order to increase a production yield has been widely employed.
FIG. 1 depicts a block diagram of a conventional column redundancy circuit. As shown in FIG. 1, a normal Y-decoder 12 and a fuse box 14 are mounted to a column segment 10, and a normal Y-decoder 22 and a fuse box 24 are mounted to a column segment 20.
The fuse boxes 14 and 24 receive a column address as an input, generate a normal column disable (NCD) signal for controlling corresponding normal Y-decoders 12 and 22 according to a defectiveness of a corresponding column address, and controls spare column lines sy&lt;0&gt; and sy&lt;1&gt;, respectively.
The normal Y-decoders 12 and 22 receive a column address as well as the normal column disable (NCD) signal generated from corresponding fuse boxes 14 and 24, decode the column address and the normal column disable (NCD) signal, and then control corresponding column lines cy&lt;0:(m-1)&gt; and cy&lt;m:(2m-1), respectively.
According to the aforementioned column redundancy circuit, a normal column line cyi is enabled in a normal state, and a spare column line syi is enabled in a repair state. This is determined according to whether a fuse inside of fuse boxes 14 and 24 is blown or not.
For example, as shown in FIG. 2A which shows signal waveforms employed to a column enable operation when a normal state is determined in FIG. 1, if a column address being input to the fuse boxes 14 and 24 and to the normal Y-decoders 12 and 22 is enabled, a normal column disable (NCD) signal generated from the fuse boxes 14 and 24 drops from a high pre-charge state to a low pre-charge state. The normal Y-decoders 12 and 22 receive a normal column disable (NCD) signal of the low precharge state as an input, and enable a normal column line cyi corresponding to the input column address. At this time, a spare column line syi maintains a low state.
As shown in FIG. 2B which shows signal waveforms employed in a column enable operation when a repair state is determined in FIG. 1, if a column address being input to the fuse boxes 14 and 24 and to the normal Y-decoders 12 and 22 is enabled and is in a repair state, the normal column disable (NCD) signal generated from the fuse boxes 14 and 24 continuously maintains a high precharge state, thus the column line cyi is not enabled while the spare column line syi is enabled.
According to the conventional column redundancy circuit, if the normal column (Y) line is enabled, the normal Y-decoder receives an output signal of the fuse box as an input, and enables a corresponding column line. In addition, in a redundancy state, the normal Y-decoder enables a repair column line on the basis of the output signal of the fuse box, thereby causing a problem in lowering an operation speed of a column line.
In order to obviate such problem, U.S. Pat. No. 5,495,445, entitled "REDUNDANCY SCHEME FOR MEMORY CIRCUITS", is provided in which content of a selected equivalent redundant element is prior to a content of a defective element.
In other words, the U.S. Pat. No. 5,495,445 senses the location of a defective element and programs a circuit to allow a corresponding redundant element to be selected when the defective element is addressed. If the defective element is addressed, defective information is provided on a data line, and accurate information provided on the data line by a redundant element corresponding to the defective element appears prior to the defective information. As a result, normal and redundancy columns are simultaneously enabled, wherein the redundancy column overwrites the normal column.
As to the operations of the U.S. Pat. No. 5,495,445, a normal column and a redundancy column are simultaneously enabled when a redundancy column address is input. In this case, a bit line sense-amp of the normal column and a bit line sense-amp of the redundancy column are simultaneously operated, and the data generated from the two bit line sense-amps is outputted to the outside via one data line commonly connected to the two bit line sense-amps. In this case, a driving ability of a signal generated from the redundancy column is increased, so that an input/output sense-amp generates a signal of the redundancy column.
However, since the data line is not divided in the U.S. Pat. No. 5,495,445, the U.S. Pat. No. 5,495,445 employs a fighting structure wherein a collision between the data of the normal column and the data of the redundancy column occurs in case that the data of the normal column and the data of the redundancy column are simultaneously generated. Since an electric potential of the data line is determined by a fighting operation, a complete repair operation is not achieved in case of an error such as a connection between the data line and a power line.